(1) Field of the Invention
The present invention relates to split-gate memory cells used in flash EEPROMs (Electrically Erasable Programmable Read Only Memories), and in particular, to a method of forming a poly tip in split-gate flash cells.
(2) Description of the Related Art
Programming (coding) and erasing (decoding) of memory cells is accomplished by tunneling of electrons through the thin oxide between the substrate and the floating gate in a split-gate flash memory cell. The effectiveness of the program/erase modes, that is, the speed with which they can be performed, can be enhanced by providing a protrusion for the floating gate of the split-gate cell. Normally, the protrusion is formed by poly oxidation, that is, by oxidizing the polysilicon of which the floating gate comprises; That is, the oxidized portion of the poly-gate is used as a hard mask to form a protruding, so-called gate bird""s beak (GBB), or, a tip, which in turn enhances the well-known Fowler-Nordheim (F-N) tunneling for the programming and erasing of an EEPROM cell. However, thick poly is needed in order to grow a thick poly-oxide hard-mask. Thick poly, on the other hand, increases gate coupling ratio (GCR), a parameter which is well-known in the art. Increased GCR then degrades the programming and erasing function of the cell. Especially, with the fast pace of miniaturization and scaling down of devices, it s becoming more and more difficult to form thick poly-oxides because of the oxide thinning effect.
Furthermore, the forming of a GBB must be optimized carefully, for, otherwise, the GBB can encroach under the gate edge and degrade the programmability of submicron memory cells. That is, the dimensions and shape of the GBB, which is described below more in detail in relation to nonvolatile memories, play an important role in transferring current to and fro between the substrate and the floating gate, and hence the charging speed of the memory cell, and the amount of surface current leakage that takes place around and near the bird""s beak. It is disclosed in this invention a method of forming a poly tip, in place of the conventional GBB, by forming a tapered floating poly-gate, whereby the tip is more controllable and sharper and therefore the program/erase mode of the split-gate flash memory cell is more enhanced.
The shape and size of different portions of memory cells have different effects on the performance of the memory cells in different ways. Thus, with the one-transistor memory cell, which contains one transistor and one capacitor, many variations of this simple cell have been advanced for the purposes of shrinking the size of the cell and, at the same time, improve its performance. The variations consist of different methods of forming capacitors, with single, double or triple layers of polysilicon, and different materials for the word and bit lines. Another variation which is disclosed in this invention relates to the tapered shape of the edge of the floating gate which significantly affects the erase speed of split-gate flash memory cells.
Memory devices include electrically erasable and electrically programmable read-only memories (EEPROMs) of flash electrically erasable and electrically programmable read-only memories (flash EEPROMs). Many types of memory cells for EEPROMs or flash EEPROMs may have source and drains regions that are aligned to a floating gate or aligned to spacers. When the source and drain regions are aligned to the floating gate, a gate electrode for a select transistor is separate from the control gate electrode of the floating gate transistor. Separate select and control gates increase the size of the memory cell. If the source and drain regions are aligned to a spacer formed after the floating gate is formed, the floating gate typically does not overlie portions of the source and drain regions. Programming and erasing performance is degraded by the offset between the floating gate and source and drain regions.
Most conventional flash-EEPROM cells use a double-polysilicon (poly) structure of which the well known split-gate cell is shown in FIG. 1. The forming of the cell is shown in FIGS. 2a-2f which will be described shortly. In the final form of the cell shown in FIG. 1, There, a MOS transistor is formed on a semiconductor substrate (10) having a first doped region (1), a second doped region (9), a channel region (5), a gate oxide (11), a floating gate (12), intergate dielectric layer (15) and control gate (16). Substrate (10) and channel region (5) have a first conductivity type, and the first (1) and second (9) doped regions have a second conductivity type that is opposite the first conductivity type.
As seen in FIG. 1, the first doped region, (1), lies within the substrate. The second doped region, (9), lies within substrate (10) and is spaced apart form the first doped region (1). Channel region (5) lies within substrate (10) and between first (1) and second (9) doped regions. Gate oxide layer (11) overlies substrate (10). Floating gate (12) covered by poly-oxide (14), and to which there is no direct electrical connection, and which overlies substrate (10), is separated from substrate (10) by a thin layer of gate oxide (11) while control gate (16), to which there is direct electrical connection, is generally positioned over the floating gate with intergate oxide (15) therebetween.
In the structure shown in FIG. 1, control gate (16) overlaps the channel region, (7), adjacent to channel (5) under the floating gate, (12). This structure is needed because when the cell is erased, it leaves a positive charge on the floating gate. As a result, the channel under the floating gate becomes inverted. The series MOS transistor (formed by the control gate over the channel region) is needed in order to prevent current flow from control gate to floating gate. The length of the transistor, that is the overlap of the control gate over the channel region (7) determines the cell performance. Furthermore, the shape of the edge (3) and, in particular, that of edge (13) can affect the programming of the cell. It is disclosed in this invention that the edge (13) can be shaped differently to have a sharp and robust tip. This is accomplished by forming a tapered floating gate as disclosed later in the embodiments of the present invention.
To program the transistor shown in FIG. 1 which shows the placement of gate, source and drain voltages or Vg, Vs and Vd, respectively, charge is transferred from substrate (10) through gate oxide (11) and is stored on floating gate (12) of the transistor. The amount of charge is set to one of two levels to indicate whether the cell has been programmed xe2x80x9conxe2x80x9d of xe2x80x9coff.xe2x80x9d xe2x80x9cReadingxe2x80x9d of the cell""s state is accomplished by applying appropriate voltages to the cell source (1) and drain (9), and to control gate (16), and then sensing the amount of charge on floating gate (2). To erase the contents of the cell, the programming process is reversed, namely, charges are removed from the floating gate by transferring them back to the substrate through the gate oxide.
This, programming and erasing of an EEPROM is accomplished electrically and in-circuit by using Fowler-Nordheim (F-N) tunneling as is well known in prior art. Basically, a sufficiently high voltage is applied to the control gate and drain while the source is grounded to create a flow of electrons in the channel region in the substrate. Some of these electrons gain enough energy to transfer from the substrate to the floating gate through the thin gate oxide layer by means of Fowler-Nordheim tunneling. The tunneling is achieved by raising the voltage level on the control gate to a sufficiently high value of about 12 volts. As the electronic charge builds up on the floating gate, the electric field is reduced, which reduces the electron flow. When, finally, the high voltage is removed, the floating gate remains charged to a value larger than the threshold voltage of a logic high that would turn it on. Thus, even when a logic high is applied to the control gate, the EEPROM remains off. Since tunneling process is reversible, the floating gate can be erased by grounding the control gate and raising the drain voltage, thereby causing the stored charge on the floating gate to flow back to the substrate. And, as stated earlier, the gate bird""s beak (GBB) is known to enhance F-N tunneling.
In prior art, protrusions other than GBB have been used to enhance the operation of flash memory cells. For example, Kesthood in U.S. Pat. No. 5,476,801 discloses a sharp tip formed on a poly spacer in order to affect erase operation by tunneling electrons from the tip to the control. gate of the cell. The cell is formed by forming the drain regions into the substrate through openings in a first insulator that is preferably the field oxide. A second insulator is deposited over the first insulator, over the substrate and along the side-walls of the openings and is preferably a thin layer so that the opening is covered with a thin insulating layer. The insulated opening is filled with a first doped polysilicon layer. The field oxide is selectively removed. A gate oxide is grown and a second polysilicon layer is formed and then etched to form spacers along the edges of the first polysilicon/second insulator structure. The second polysilicon is selectively etched and a tunneling insulator layer is formed thereover. A third polysilicon layer is formed over the tunneling insulator.
Baglee in U.S. Pat. No. 4,975,384, on the other hand, discloses an EEPROM cell using trench edge tunneling. The trench has bottom corners sufficiently sharp so as to enhance the likelihood of tunneling between corner regions of the trench and the floating gate over that between planar surface regions of the trench and floating gate. In still another approach, Wang, in U.S. Pat. No. 5,597,751 teaches a method of forming a memory cell where there is no shorting problem between a floating gate and a source/drain region of the substrate of the cell by depositing a thick spacer oxide layer on top of the floating gate and the source/drain region to a sufficient thickness such that electrical insulation is provided thereinbetween.
In still a different approach, Cho, et al., in U.S. Pat. No. 5,766,988 show a method of fabricating a thin film transistor with a negatively sloped gate. According to Cho, et al., a thin film transistor may include an insulation substrate, a gate electrode formed to have a negative slope at one side thereof on the insulation substrate, an insulation film side-wall formed at the other side of the gate electrode, a gate insulation film formed on the insulation substrate, gate electrode and side-wall, a semiconductor layer formed on the gate insulation film, impurity diffusion regions selectively formed within the semiconductor layer over the gate electrode, the side-wall and the insulation substrate on the other side of the gate electrode, and a channel region formed within the semiconductor layer at the side of the gate electrode having the negative slope.
It is disclosed in this invention a simpler and different method of forming sloped or tapered side-walls on the floating gate of a split-gate flash memory cell for the purposes of forming a sharper poly tip on the same floating gate.
It is therefore an object of this invention to provide method of forming a sharp poly tip to improve erase speed in split-gate flash memory.
It is another object of this invention to provide a method of forming a tapered floating gate in a split-gate flash memory.
It is yet another object of this invention to provide a method of etching an opening in a nitride layer to have a tapered sidewall in a split-gate flash.
It is still another object of the present invention to provide split-gate flash memory cell having a sharp poly tip on the tapered floating gate of the cell.
These objects are accomplished by providing a silicon substrate having a plurality of active and field regions defined; forming a pad oxide layer over said substrate; forming a nitride layer over said pad oxide layer; forming forming a nitride layer over said pad oxide layer; forming and patterning a first photoresist layer over said pad oxide layer to form a photoresist mask with a pattern corresponding to the floating gate of said split-gate flash memory cell; etching said nitride layer through said photoresist mask to form an opening with a tapered profile reaching said pad oxide layer underlying said nitride layer; removing said first photoresist layer; removing said pad oxide layer exposed at the bottom of said opening with a tapered profile in said nitride layer; growing gate oxide layer at the bottom of said opening with said tapered profile in said nitride layer; forming a first polysilicon layer over said substrate including said opening with a tapered profile; performing chemical-mechanical polishing (CMP) of said first polysilicon layer; oxidizing said fist polysilicon layer formed in said opening with a tapered profile, thus forming a sharp poly tip at the edge of said opening; removing said nitride layer; removing said pad oxide layer; forming an interpoly oxide layer over said substrate; forming a second polysilicon layer over said interpoly oxide; and patterning said second polysilicon layer with a second photoresist mask having control gate pattern to form a control gate to complete the forming of said split-gate flash memory cell having said sharp poly tip.
These objects are further accomplished by providing a split-gate flash memory cell having a sharp poly tip formed on the tapered wall of the floating gate of a split-gate flash memory cell.